/*
 * @(#)XfvhdlRulesMemFileWithROM.java        3.0             2004/09/14
 *
 * This file is part of Xfuzzy 3.0, a design environment for fuzzy logic
 * based systems.
 *
 * (c) 2000 IMSE-CNM. The authors may be contacted by the email address:
 *                    xfuzzy-team@imse.cnm.es
 *
 * Xfuzzy is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by
 * the Free Software Foundation.
 *
 * Xfuzzy is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 */

package xfuzzy.xfvhdl;

import xfuzzy.lang.*;
import java.io.*;

/**
* Clase que genera el fichero de la memoria de reglas RulesMem.vhdl 
* usando una memoria ROM.
* @author Jos� Mar�a �vila Maireles, <b>e-mail</b>: josavimai@alum.us.es
* @version 3.0
*/
public class XfvhdlRulesMemFileWithROM implements XfvhdlIRulesMem {

	//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
	//			  M�TO_DOS P�BLICOS DE LA CLASE				       
	//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
	/**
	* M�todo que crea la cadena que ser� escrita en fichero 
	* RulesMem.vhdl usando una memoria ROM.
	* @return Devuelve la cadena que ser� escrita en fichero 
	* RulesMem.vhdl usando una memoria ROM.
	*/
	public String createRulesMemSource(Specification spec) throws IOException {

		XfvhdlRulesMemData contenido =
			new XfvhdlRulesMemData(
				XfvhdlProperties.dir_regl,
				XfvhdlProperties.N,
				XfvhdlProperties.K,
				spec);

		XfvhdlHeadFile head =
			new XfvhdlHeadFile(
				XfvhdlProperties.fileDir,
				XfvhdlProperties.outputFile + "RulesMem.vhdl",
				XfvhdlProperties.ficheroXFL);

		String code = head.getHead();

		code
			+= "\n--***********************************************************************--\n"
			+ "--                                                                       --\n"
			+ "--   DESCRIPTION: This file contains the VHDL description for the        --\n"
			+ "--                rules memory of the fuzzy controller.                  --\n"
			+ "--                                                                       --\n"
			+ "---------------------------------------------------------------------------\n"
			+ "--                                                                       --\n"
			+ "--   AUTHOR:      Jose Maria Avila Maireles                              --\n"
			+ "--                                                                       --\n"
			+ "--   VERSION:     Xfvhdl  ver0.1                          January 2004   --\n"
			+ "--                                                                       --\n"
			+ "--***********************************************************************--\n"
			+ "\n"
			+ "\n"
			+ "library IEEE;\n"
			+ "use IEEE.std_logic_1164.all;\n"
			+ "use IEEE.std_logic_unsigned.all;\n"
			+ "\n"
			+ "use WORK.Constants.all;\n"
			+ "\n"
			+ "\n"
			+ "---------------------------------------------------------------------------\n"
			+ "--                           Entity description                          --\n"
			+ "---------------------------------------------------------------------------\n"
			+ "\n"
			+ "entity RulesMem is\n"
			+ "\n"
			+ "\tport(\taddr\t: in std_logic_vector(dir_regl downto 1);"
			+ "\t\t-- Address bus\n"
			+ "\t\tme\t: in std_logic;\t\t\t\t\t\t-- Memory enable\n"
			+ "\n"
			+ "\t\tdo\t: out std_logic_vector(w_reglas downto 1));"
			+ "\t-- Data bus\n"
			+ "\n"
			+ "end RulesMem;\n"
			+ "\n"
			+ "\n"
			+ "---------------------------------------------------------------------------\n"
			+ "--                       Architecture description                        --\n"
			+ "---------------------------------------------------------------------------\n"
			+ "\n"
			+ "architecture FPGA of RulesMem is\n"
			+ "\n"
			+ "\tsignal data: std_logic_vector(w_reglas downto 1);\n"
			+ "\n"
			+ "\tsubtype ROM_WORD is std_logic_vector(w_reglas-1 downto 0);\n"
			+ "\ttype ROM_TABLE is array (0 to reglas-1) of ROM_WORD;\n"
			+ "\tconstant ROM: ROM_TABLE := ROM_TABLE'(\n";

		XfvhdlBinaryDecimal converter = new XfvhdlBinaryDecimal();

		for (int i = 0; i < contenido.getLength() - 1; i++) {
			if (contenido.isActive(i))
				code += "\t\t\tROM_WORD'(\""
				//+ contenido.getLine(i)
				+"" + contenido.getValue(i) + "\"),\n";
			else
				code += "\t\t\tROM_WORD'(\""
				//+ contenido.getLine(i)
				+"" + converter.toHyphen(XfvhdlProperties.w_reglas) + "\"),\n";
		}

		// La �ltima l�nea es especial porque hay que ponerle 
		// un parentesis al final.
		if (contenido.isActive(contenido.getLength() - 1))
			code += "\t\t\tROM_WORD'(\""
			//+ (contenido.getLine(contenido.getLength() - 1))
			+"" + (contenido.getValue(contenido.getLength() - 1)) + "\"));\n";
		else
			code += "\t\t\tROM_WORD'(\""
			//+ (contenido.getLine(contenido.getLength() - 1))
			+"" + converter.toHyphen(XfvhdlProperties.w_reglas) + "\"));\n";

		code += "\tbegin\n"
			+ "\n"
			+ "\t\tdo <= ROM(conv_integer(addr));\n\n"
			+ "end FPGA;";

		return code;
	}

} // Fin de la clase
